Half-day Tutorial: Open Hardware Networking
Monday 17th August, Morning Session
Presenters
Noa Zilberman, University of Cambridge
Gianni Antichi, University of Cambridge
Charalampos Rotsos, Lancaster University
Tutorial location
The tutorial will take place in Huxley Building, room LT308. For directions inside Imperial College check the campus map (building number 13).
Tutorial timetable
08:30 Coffee and danish pastries
09:00 Tutorial start
10:30-11:00 Coffee break
12:30 Tutorial finish
12:30-14:00 Buffet lunch
Abstract
The demand-led growth of cloud computing and datacenter networks has meant that many constituent technologies are beyond the budget of the research community. In order to make and validate timely, relevant research contributions, the wider research community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks.
This tutorial will introduce rapid device prototyping and testing in open source, that is accessible to researchers with a wide set of skills: From networking-hardware researchers, through protocol researchers to experts in formal methods.
Outline
- NetFPGA
- Background
- NetFPGA Update
- Hardware Overview
- NetFPGA SUME
- Rapid prototyping of a simple networking device
- Demonstration
- Getting started and what to do next
- Challenges in Network Testing
- OSNT - Open Source Network Tester
- Traffic generation
- Traffic monitoring
- Device testing with OSNT
- SDN and Performance
- Dataplane performance
- OpenFlow consistency
- OFLOPS-Turbo
- Architecture
- APIs
- Sample execution
- Concluding Remarks
——— Coffee Break ———
Expected Audience and Prerequisites
The target audience is not restricted to hardware researchers: open hardware networking provides the ideal platform for research across a wide range of networking topics from architecture to algorithms and from energy-efficient design to routing and forwarding. It is thus ideally suited for any attendees of SIGCOMM.
No knowledge of Verilog/VHDL is required to attend the tutorial.
Related information
Bios
Noa Zilberman is a Research Associate at the University of Cambridge Computer Laboratory in England, where she is part of the Systems Research Group and works on reconfigurable network systems. Zilberman has over 15 years of industrial experience in the telecommunication and semiconductor industries. In her last role, she was a senior principal chip architect in Broadcom’s Infrastructure group. Her research interests include high-performance networking and computing architectures, high-speed interfaces, network measurements and Internet topology. Zilberman is a Senior Member of IEEE and has a PhD in Electrical Engineering from Tel-Aviv University.
Gianni Antichi is a Research Associate at University of Cambridge Computer Lab in England, where he is part of the Systems Research Group. Since the end of 2012, he has been part of the NetFPGA DEV team. His research interests are in the area of hardware-accelerated networking systems, network design, network monitoring, packet classification and Software-Defined Networks. He has co-authored more than 20 papers presented in leading international journals and conferences.
Charalampos Rotsos is a Senior Research Associate at Lancaster University School of Computing and Communications in England, and he is part of the Network Research Group. His research interests are in the area of Software-Defined Networking, network experimentation, network measurement and traffic classification.
