Full-Day Tutorial. P4: Programming the Network Dataplane
Friday 21st August
Changhoon Kim, LJ Wobker, and Antonin Bas
Panelists for the mini workshop: Nick Feamster (Princeton), Minlan Yu (USC), Mukesh Hira (Vmware), and Peter Hoose (FaceBook)
The tutorial will take place in Sherfield Building, room SALC 6. For directions inside Imperial College check the campus map (building number 20).
08:30 Coffee and danish pastries
09:00 Tutorial start
10:00-10:30 coffee break
12:30-14:00 buffet lunch
15:30-16:00 coffee break
17:00 Tutorial finish
We all know how to program a CPU, making it easy to create new programs, prototype new ideas, build new applications and share them with others. Today, it is commonplace to program general-purpose CPUs, GPUs, and even DSPs – the programmer describes the desired behavior in a high-level language, which is compiled down to run on a domain-specific processor. We have seen this story repeating many times in the history of computing over several types of processors.
In networking, this story is just unfolding. Software-Defined Networking (SDN) is reshaping the way we design, build, and run networks by enabling those who own and operate networks to program network behavior. SDN’s programmability, however, is still confined to the network control plane. The network data plane (i.e., packet forwarding logic) is still largely dictated by fixed-function switching chips. But this is changing quickly: Nowadays, FPGAs and NPUs can be used to build programmable forwarding devices with mid-range performance (up to a few hundred Gb/s). At the high-end of performance, new programmable protocol-independent switch chips promise multi Tb/s of packet processing [1, 2, 3]. And of course at the low-end of performance, CPUs and GPUs offer great flexibility with performance of a few tens of Gb/s (e.g. hypervisor switches, server NICs with hardware offload processing).
P4 (www.p4.org) was created as a common language to describe how packets should be processed by all manner of programmable switches, from low-end CPUs to high-end ASICs . P4 was designed with three goals:
- Protocol independence: Network devices should not be tied to any specific network protocols.
- Target independence: Programmers should be able to describe packet-processing functionality independently of the specifics of the underlying hardware.
- Re-configurability in the field: Programmers should be able to change the way switches process packets once they are deployed.
The P4 community has created – and continues to maintain and develop – a language specification, and a set of open-source tools (compilers, debuggers, code analyzers, libraries, run-time simulators, etc.) with the goal of making it easy to quickly and correctly author new network behaviors. New ideas are already being authored using P4 (examples include CONGA , Tiny Packet Programs , OpenSketch , DUET , and the P4 compiler paper ), prototyped as new forwarding behaviors, and published at top networking conferences. Existing data-plane features typically realized in a hard-wired logic (such as AQM schemes - WRED , CoDel , congestion control schemes - ECN and its variants, and network monitoring functions - sFlow) are also being authored in P4.
The main goal of the tutorial is to enable attendees to use P4 in their research, to prototype their ideas and run them in programmable switches. We also aim to encourage researchers and developers to contribute to the P4 language, and develop new tools (e.g. compilers, debuggers, formal verification tools). Via a hands-on tutorial, we will teach attendees how to write functioning P4 programs to implement existing and new protocols, and to add new functionality in the forwarding plane. By the end of the tutorial attendees will be able to implement novel data-plane features in P4, and evaluate their programs in a Mininet emulation framework.
More specifically, this tutorial will provide participants with the followings:
- Introduction to P4
- Introduction to reference P4 programs that realize most well-known data-plane functions, such as L2 and L3 forwarding (including unicast, multicast, and broadcast), ARP, MPLS, ACLs, ECMP, LAG (link-aggregation), various forms of en/decapsulation and address translations.
- Introduction to P4 development tools: compilers, debuggers, P4 abstract machine (a S/W switch programmable in P4), etc.
- Demonstrations of the existing and new networking features developed in P4.
- Panel to share P4-programming experiences in research, engineering, and teaching projects.
A full-day event comprised of the followings:
- Lecture on P4 (1.5hr)
- Demonstration of existing and new networking features developed in P4 (0.5hr)
- Hands-on training of P4 development environment (compiler, debugger, behavioral model) (2.5hr)
- Panel (1.5hr)
- Exchanging P4-programming experiences for research & teaching project
- Panel discussing research topics regarding novel data-plane protocols, programming models, and development environment
Expected Audience and Prerequisites
The tutorial will be useful to researchers, students, and practitioners alike (engineers, network admins, network architects, and developers).
Attendees must bring their own laptops. We will provide a VM image containing all the necessary packages and tools.
The P4 spec is publicly available at www.p4.org under an Apache-style license. Several key development tools (front-end compiler and s/w switch capable of running P4 programs) are already available as open source.
Changhoon Kim is Director of System Architecture at Barefoot Networks and is working actively for the P4 Language Consortium (P4.org). Before getting involved with P4.org and Barefoot, he worked at Windows Azure, Microsoft’s cloud-service division, and led engineering and research projects on the architecture, performance, and management of datacenter networks. Chang is interested in programmable network dataplane, network monitoring and diagnostics, network verification, self-programming/configuring networks, and debugging and diagnosis of large-scale distributed systems. Chang received Ph.D. from Princeton University. Many of his research contributions — including VL2, Seawall, EyeQ, Ananta, and SEATTLE — are adopted in large production networks.
Lawrence “LJ” Wobker is a TME at Barefoot Networks. Prior to Barefoot, he worked for 15+ years at Cisco Systems in a variety of engineering roles including operations support for some of the world’s largest provider and data-center networks, design services for large scale enterprise networks, and many years focusing on system design and architecture for extremely large-scale routing and switching systems. His main areas of technical focus are building and optimizing forwarding planes based on microcoded and other programmable ASICs and NPUs, FIB design, and traffic management and QoS designs at both the device and network level. Lawrence holds a BS in Computer Science from North Carolina State University.
Antonin Bas is a Software Engineer at Barefoot Networks, where he contributes to the development of several P4 software tools. He is the lead contributor of the original P4 software switch, which is open-sourced through P4.org in April 2015. Antonin holds a M.S. in Computer Science from Stanford University and a M.S. in Engineering from the Ecole Polytechnique, in France.
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