Workshop on Formal Foundations and Security of Programmable network INfrastructures (FFSPIN)

Workshop Program

Monday August 22, 2022 CEST (Room: Verwey kamer)
9:00 - 9:50 am CEST Opening + Keynote
Tea/Coffee/Meal Break

9:00 - 9:10 am CEST

Opening Remarks

Speakers: Workshop co-chairs

9:10 - 9:50 am CEST

Keynote: When network programmability meets network security: the good, the bad and the ugly

Speaker: Laurent Vanbever (ETH Zurich)
Abstract: Is having a programmable network necessarily good from a security viewpoint? The answer, I think, is multifaceted. On the plus side, programmable networks enable to protect, prevent, and defend against attacks in unprecedented ways. On the minus side though, programmable networks also enable to perpetrate new types of attacks and can become attractive targets themselves. Figuring out a way to reap the benefits of network programmability while minimizing the drawbacks is therefore an important research question.
In this talk, I will present some of our research in the area. I will first talk about the [good] aspects of programmability, and how programmable networks can prevent attackers from: inferring network topologies, analyzing traffic, or performing DDoS attacks. I will then speak about the [bad] aspects of programmability, and how programmable networks can be misused to perpetrate new types of DDoS attacks. Finally, I will mention some (perhaps more) [ugly] aspects of programmable networks, and how they can be abused simply by sending crafted packets.

09:50 - 10:30 am CEST Invited Talk 1

9:50 - 10:30 am CEST

Title: The next 700 network switches

Speaker: Fernando Ramos (Instituto Superior Técnico, Universidade de Lisboa)
Abstract: In this talk I will motivate and present the rationale for new data plane primitives for network switches that are enabling a range of new applications, in particular to improve network security. To address specific limitations of current PISA-based programmable switches, several recently proposed data plane architectures augment these switches with primitives for floating point operations, finite field arithmetic, and ML inference, to name a few. I will share some thoughts on how this trend may potentially lead to a variety of “specialised" network switches that incorporate different sets of primitives, and discuss some of the challenges ahead.

10:30 - 11:00 am CEST Coffee Break
Break
11:00 am - 12:30 pm CEST Paper presentations

Session chair: Diogo Barradas

IoT MUD Enforcement in the Edge Cloud Using Programmable Switch

Harish S A, Hemanth Kothapalli, Shubham Lahoti, Kotaro Kataoka, Praveen Tammana (Indian Instituteof Technology Hyderabad)

PISketch: Finding Persistent and Infrequent Flows

Zhuochen Fan, Zhoujing Hu, Yuhan Wu, Jiarui Guo, Wenrui Liu, Tong Yang, Hengrui Wang (PekingUniversity); Yifei Xu (University of California, Los Angeles); Steve Uhlig (Queen Mary University ofLondon); Yaofeng Tu (ZTE Corporation)

Implementing ChaCha Based Crypto Primitives on Programmable SmartNICs

Shaguftha Zuveria Kottur (Indraprastha Institute of Information Technology Delhi); Krishna Kadiyala(Texas Christian University); Praveen Tammana (Indian Institute of Technology Hyderabad); Rinku Shah(Indraprastha Institute of Information Technology Delhi)

P4-DPLL: Accelerating SAT Solving Using Switching ASICs

Jinghui Jiang, Zhenpei Huang, Qiao Xiang, Lu Tang, Jiwu Shu (Xiamen University)

12:30 - 1:30 pm CEST Lunch Break
Lunch Break
1:30 - 3:00 pm CEST Invited Talk 2

1:30 - 3:00 pm CEST

Title: Modular Verification of the Evolving Internet

Speaker: Pamela Zave (Princeton University) and Jennifer Rexford (Princeton University)
Abstract: Network verification has had notable successes, but its potential is currently limited by a low level of abstraction and reliance on an outdated model of Internet architecture. In this talk, we introduce a new model of the real Internet architecture that explains its evolution and exposes its natural modularity. Examples show that this modularity can be exploited to verify properties of network behavior as experienced by users, in an efficient and scalable manner. We believe that the new model can serve as a foundation for a community of researchers who are able to make faster progress on the issues that are most important for the future of the Internet.

3:00 - 3:30 pm CEST Coffee Break
Break
3:30 - 4:50 pm CEST Panel Discussion

3:30 - 4:50 pm CEST

Panel

Panelists: Paola Grosso (University of Amsterdam), Pamela Zave (Princeton University), Mohammad Mousavi (King's College London)

4:50 - 5:00 pm CEST Closing Remarks
Tea/Coffee/Meal Break

4:50 - 5:00 pm CEST

Closing Remarks

Speaker: Workshop co-chairs

Call for Papers

The Internet was not designed with a secure foundation. However, as more and more applications rely on secure network services, the importance of network security has grown significantly. Looking forward, studying the security of networks and networked systems will become a first-class design goal. In tandem, the study of formal methods for the rigorous design and verification of networks takes increased relevance towards avoiding network failures and enabling the construction of correct-by-design networks. Up until recently, one hindrance in designing secure and correctly functioning networks was that the Internet was very hard to change. Networking devices used to be “blackboxes”, and only the switch vendors can decide what goes into these boxes. Despite multiple proposals to enhance Internet/network security, many of these useful designs lacked formal specification and verification, or could not be easily integrated into the operational network without a forklift change.

Recently, a new opportunity is on the horizon---networking hardware is becoming programmable. The networking community has already leveraged this to design a range of new systems and capabilities “in-network”, but we argue that it is important to rethink network security, specification, and verification in light of this trend as well.

The 3rd FFSPIN workshop (a joint effort between the previous SPIN and FoFoSDN workshops) aims to provide a forum for the community to come together and rethink fundamental questions in programmable networks and Internet security. In this workshop, we are soliciting papers that examine the security implications and formal foundations of the trend of network programmability, particularly in the recent development of programmable data planes. We seek contributions on early ideas in these areas, position papers that outline next steps in network security, as well as preliminary papers from ongoing projects that could benefit from early community feedback. The workshop seeks to bring together experts in networking, security, hardware, formal specification and verification, programming languages, and systems, with the goal of reexamining opportunities for programmable networks in the next generation.

Topics of Interest

Topics of interest include, but are not limited to:

Security applications of programmable networking hardware (e.g., programmable switches, smartNICs)
Security applications of network function virtualization
Privacy-preserving programmable communication networks
The security risks of programmable networking hardware
Intrusion and anomaly detection and prevention
Denial-of-service attacks and countermeasures
Deployable or backward-compatible designs for network security
Architectural support for Internet/network security
Role of programmable optics for network security
Cross-layer programmability and software-defined infrastructures for network security
Policies for Internet security
New environments that require network programmability (e.g., IoT, Smart Homes, Multi-tenant datacenters, Satellite networks) that could benefit from secure programmable infrastructures
Incrementally deployable designs for secure programmable networks
Formal models for software-defined networking and programmable networks
Validation, verification, testing, and learning techniques for software-defined networking and programmable networks

Submission Instructions

Submissions must be original, unpublished work, and not under consideration at another conference or journal. LaTeX sources can be found at this link [https://github.com/scyue/latex-sigcomm18]. With older versions of this template, authors should use "10pt" in the documentclass command to ensure that the font size for all submitted papers is 10 points. The length of the submitted paper should be 6 pages, excluding references. Authors are welcome to include an appendix beyond the page limit, but the main paper should be self-contained. Paper submissions should not include author names or affiliations, and submissions will go through a double-blind reviewing process by the program committee. At least one author for each accepted paper is expected to present the paper at the workshop in person. We expect that at least some papers at FFSPIN would represent "work-in-progress" projects. Therefore, authors of published papers could choose to extend their work to full-length conference papers later.

Please submit your paper via https://ffspin22.hotcrp.com.